Scott Beamer

Scott Beamer

Associate Professor

Computer Science and Engineering

University of California, Santa Cruz

sbeamer@ucsc.edu

Office: Engineering 2 Room 229

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I design architectures for data-intensive applications, with a focus on improving communication efficiency. I am interested in: computer architecture, agile and open-source hardware design, graph processing, and data movement optimization. I lead the Vertical Architectures, Memory, and Algorithms (VAMA) group, and we are part of the Hardware Systems Collective.

I completed my PhD in Computer Science at UC Berkeley while creating the GAP Project and contributing early to RISC-V. Previously, I was a postdoctoral fellow at Lawrence Berkeley National Lab in the Computer Architecture Group. I received an NSF CAREER Award in 2022.

Teaching

Students

I have the good fortune to be working with:

I am grateful to have worked with our group alumni:

I am the coach for UCSC's student cluster team, the Not So Slow Slugs. The team has competed twice in the virtual ISC (2nd in 2023), twice in the IndySCC, and four times in the Winter Classic Invitational (3rd in 2021, 2nd in 2023, 2nd in 2024, 2nd in 2025).

Research

My research focuses on improving communication efficiency, since for many data-intensive workloads, accessing the necessary data (communication) is often a bigger challenge than the computation itself. For these communication-bound workloads, optimizing communication can bring many benefits, whether it be improved performance, decreased energy consumption, or reduced manufacturing cost. Much of my work focuses on graph processing, as its data-intensive nature exposes many communication challenges. Going forward, I'm excited to bring my approach to other computational patterns and application domains.

To improve communication efficiency, one can either reduce the amount of communication (move less data) or accelerate the rate of communication (increase utilized bandwidth). My research utilizes both approaches, and I apply them by optimizing software or designing new hardware. To guide these optimization efforts, I analyze the workload to identify bottlenecks. To more aggressively improve hardware communication efficiency, I also investigate the best ways to leverage new technologies such as monolithically integrated silicon photonics.

Publications

By Date | By Type | By Topic

Professional Service

Funding Acknowledgements

I am grateful to the following organizations that support my group: University of California, Intel, National Science Foundation, Amazon Web Services, Xilinx, and GitHub.